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Configuration Bits 18F4550

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  • Configuration Bits 18F4550

    I am not new to PBP, but have been using mplab and sourceboost for a good while now and am trying to get bakc to this. I am struggling to get the configuration bits changed. I found the information at http://melabs.com/support/config_defaults.htm and it was completely useless. I tried every one of the methods listed and none of them worked. I got errors every time.

    The compliler is using mpasm suite (I get the black cmd screen). I have NOT included any of the .inc files as each time I do I get a compiler crash at the LIST line. I get no errors with it so I don't even know what that means. I have seen the error that says its overwriting data at whatever address, but the config bits are not actually changed (I can prove this when I load the hex file into the pickit programmer).

    How do I actually set these things? Can somebody post a snippet of code that actaully works? Please?

  • #2
    The method was changed with PBP 3.0. If you're seeing a black screen, you probably have a much older version. Is this so?
    Charles Leo
    ME Labs, Inc.
    http://melabs.com

    Comment


    • #3
      Doh! Just realized you posted in the 2.60 forum, so I can guess your version. I believe the code below will work, but I have some doubt about your version of MPASMWIN. It might not support the CONFIG directive.

      To avoid an assembly error, you'll also need to comment the existing defaults from the file 18F4550.INC in the PBP installation folder.

      For anyone using PBP 3.0 and later, use the #CONFIG directive and ignore the note about modifying the file in the installation.

      Code:
      ASM
          CONFIG  PLLDIV = 5            ; Divide by 5 (20 MHz oscillator input)
          CONFIG  CPUDIV = OSC1_PLL2    ; [Primary Oscillator Src: /1][96 MHz PLL Src: /2]
          CONFIG  USBDIV = 2            ; USB clock source comes from the 96 MHz PLL divided by 2
          CONFIG  FOSC = HSPLL_HS       ; HS oscillator, PLL enabled (HSPLL)
          CONFIG  FCMEN = OFF           ; Fail-Safe Clock Monitor disabled
          CONFIG  IESO = OFF            ; Oscillator Switchover mode disabled
          CONFIG  PWRT = OFF            ; PWRT disabled
          CONFIG  BOR = ON              ; Brown-out Reset enabled in hardware only (SBOREN is disabled)
          CONFIG  BORV = 3              ; Minimum setting
          CONFIG  VREGEN = ON           ; USB voltage regulator enabled
          CONFIG  WDT = ON              ; WDT enabled
          CONFIG  WDTPS = 512           ; 1:512
          CONFIG  CCP2MX = ON           ; CCP2 input/output is multiplexed with RC1
          CONFIG  PBADEN = OFF          ; PORTB<4:0> pins are configured as digital I/O on Reset
          CONFIG  LPT1OSC = OFF         ; Timer1 configured for higher power operation
          CONFIG  MCLRE = ON            ; MCLR pin enabled; RE3 input pin disabled
          CONFIG  STVREN = ON           ; Stack full/underflow will cause Reset
          CONFIG  LVP = OFF             ; Single-Supply ICSP disabled
          CONFIG  ICPRT = OFF           ; ICPORT disabled
          CONFIG  XINST = OFF           ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
          CONFIG  DEBUG = OFF           ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
          CONFIG  CP0 = OFF             ; Block 0 (000800-001FFFh) is not code-protected
          CONFIG  CP1 = OFF             ; Block 1 (002000-003FFFh) is not code-protected
          CONFIG  CP2 = OFF             ; Block 2 (004000-005FFFh) is not code-protected
          CONFIG  CP3 = OFF             ; Block 3 (006000-007FFFh) is not code-protected
          CONFIG  CPB = OFF             ; Boot block (000000-0007FFh) is not code-protected
          CONFIG  CPD = OFF             ; Data EEPROM is not code-protected
          CONFIG  WRT0 = OFF            ; Block 0 (000800-001FFFh) is not write-protected
          CONFIG  WRT1 = OFF            ; Block 1 (002000-003FFFh) is not write-protected
          CONFIG  WRT2 = OFF            ; Block 2 (004000-005FFFh) is not write-protected
          CONFIG  WRT3 = OFF            ; Block 3 (006000-007FFFh) is not write-protected
          CONFIG  WRTC = OFF            ; Configuration registers (300000-3000FFh) are not write-protected
          CONFIG  WRTB = OFF            ; Boot block (000000-0007FFh) is not write-protected
          CONFIG  WRTD = OFF            ; Data EEPROM is not write-protected
          CONFIG  EBTR0 = OFF           ; Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks
          CONFIG  EBTR1 = OFF           ; Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks
          CONFIG  EBTR2 = OFF           ; Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks
          CONFIG  EBTR3 = OFF           ; Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks
          CONFIG  EBTRB = OFF           ; Boot block (000000-0007FFh) is not protected from table reads executed in other blocks
      ENDASM
      Charles Leo
      ME Labs, Inc.
      http://melabs.com

      Comment

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