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Limited support of 24f devices

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  • Limited support of 24f devices

    PBP3 supports most of the 8bit processors and the jump to 24f - to fully support 16bit would be abig one.

    but i wonder if limited support option could be made such that operations would remain 8 bit , but the larger program space only of the 24F could be used.

    mainly those chips which have larger than 128k program space

    Is this a possibility ?

  • #2
    expanding PBP3 to support a larger chip such as the 24 or 32bit - just for the programming space , is something that would be possible to do charles ?????????????????


    • #3
      We've attempted to complete this on several occasions, but there have been setbacks. The most recent attempt was stalled in 2013 due to issues concerning the developer that we were using for the PC-side executable.

      The project is bigger than an expansion of the current PBP. Some parts of the current compiler can be reused, but it's really a matter of creating a new compiler just for PIC24. The good news is that we've already completed most of the work. The issue is frequently discussed, but no development is happening right now.

      In the past, I've shared my optimism for completion dates and such. Things didn't work out. I am still optimistic, but I'm reluctant to take a guess as to what the universe holds in store. It's been a tough year.
      Charles Leo
      ME Labs, Inc.


      • #4
        yes it has been a hard year,

        i have hit the 128k boundary on a project , and even with a lot maneuvering ,

        i cant get passed the fact that there is not enough space to do all that i need to / would like , and to abandon the code to move to another is not practicable.

        i am now looking at 2 cpus , and interface overhead to get what i want to do.

        its both a setback and an opportunity i guess

        but to have the ability to move to a new chip with more code space using pbp would have been a better option , and less costly than the 2 cpu option i now face


        • #5

          Melabs lost a very important "resource". Darrel Taylor.

          Beside this a new, reliable compiler, is not an easy task.

          We all need a new compiler for 24F or even better 32F, but this will need time.

          MikroE are there, but personally I will not buy them for many reasons. I'd prefer to wait for a solid, reliable and optimized solution.



          • #6
            when 128k is not enough

            Hi Charles , was wondering if you can advise on if PBP supports the extended memory bus option on 18f87k22, will allow a compile / use well past 128k.

            the chip buss allows upto 2mb addressable , at 64mhz ( assuming the flash is quick enough )

            I was looking at using the 18f87k22 - 80 pin unit and use a feature on it for extended Memory bus , with an addtional 128k flash attached

            The new silicon of c5 solves the wait states issue


            • #7

              application notes


              • #8
                PBP was designed to allow compilation beyond the capacity of the PIC. What I don't know is how to make MPASM assemble beyond the specified limit.

                I've been squeezing code space out of a big program on the 18F87K22 for a couple of months now. If you wish, email your program to [email protected] and I'll try to spot ways to compact it further.
                Charles Leo
                ME Labs, Inc.


                • #9
                  thanks charles may do that , i tring to hammer out the design for 2 cpu solution to get past the fact of 128 limit and allow for a lot larger code in the longer term , although the interface for a 2 cpu solution will be a large overhead in either case.

                  getting a useful response from micochip on the Fmax on Extended memory bus , using 16 bit if i was to use the 18f87k22 is not happen as yet. but even on a good day it would not be 64mhz. but be nice to clarify it ,as the datasheet is not clear


                  • #10
                    lookingat the 128k limit and the use of EMB , microchip confirm that the using 16bit mode with C5 silicon ( which fixes the wait states ) the emb will fuction at 64mhz on the bus

                    using sram with a combined sram speed and glue logic of less than 21ns the EMB can allow a bootloader to copy the code to EMB and run

                    what i am not sure of how PBP would use the EMB and the code size limits in the compile ?