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TX1 Error using DT_INTS-18_3_4b on a PIC18F67K40 and UMC loader?

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  • TX1 Error using DT_INTS-18_3_4b on a PIC18F67K40 and UMC loader?

    I am looking at replacing a 67K22 ($2.98/5K) with a 67K40($1.76/5K) for large cost savings for an existing project..

    I could not download the DT_INTS-18_3_4c version to see if it corrects the error.

    DT_INTS-18_3_4b does have for the K40_family = 2 has the following define:

    #define TX1_INT PIR3, TX1IF ;-- USART1 Transmit

    TMR0, INT0, RX1,RX2, and TX2 work good if I comment out the INT_Handler TX1_INT, _ESPTXOut, PBP, yes and @ INT_ENABLE TX1_INT lines.

    On compiling I get the following error:
    "C:\PBP3\pbpx.exe" -ampasmx -c -k# -os -p18f67k40 ../K40Testx.pbp
    Error[101] C:\PICSRC-WRK\MPLABX\K40-TESTX.X\K40TESTX.ASM 1197 : ERROR: (Interrupt Source (PIR3,TX1IF) not found)
    Error[101] C:\PICSRC-WRK\MPLABX\K40-TESTX.X\K40TESTX.ASM 1265 : ERROR: (INT_ENABLE - Interrupt Source not found!)


    Code:
    @ errorlevel -306
    @ errorlevel -303
    
    #CONFIG
        CONFIG FEXTOSC = OFF    ;Oscillator not enabled
        CONFIG RSTOSC = EXTOSC    ;EXTOSC operating per FEXTOSC bits (device manufacturing default)
        CONFIG CLKOUTEN = OFF    ;CLKOUT function is disabled
        ;CONFIG CLKOUTEN = ON    ;CLKOUT function is enabled
        CONFIG CSWEN = ON        ;Writing to NOSC and NDIV is allowed
        CONFIG FCMEN = ON        ;Fail-Safe Clock Monitor enabled
        CONFIG MCLRE = EXTMCLR    ;If LVP = 0, MCLR pin is MCLR; If LVP = 1, RE3 pin function is MCLR
        CONFIG PWRTE = OFF        ;Power up timer disabled
        CONFIG LPBOREN = OFF    ;ULPBOR disabled
        CONFIG BOREN = ON        ;Brown-out Reset enabled according to SBOREN
        CONFIG BORV = VBOR_245    ;Brown-out Reset Voltage (VBOR) set to 2.45V
        CONFIG ZCD = OFF        ;ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON
        CONFIG PPS1WAY = OFF    ;PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence)
        CONFIG STVREN = ON        ;Stack full/underflow will cause Reset
        CONFIG DEBUG = OFF        ;Background debugger disabled
        CONFIG XINST = OFF        ;Extended Instruction Set and Indexed Addressing Mode disabled
        CONFIG WDTCPS = WDTCPS_31        ;Divider ratio 1:65536; software control of WDTPS
        CONFIG WDTE = OFF        ;WDT enabled regardless of sleep
        CONFIG WDTCWS = WDTCWS_7        ;window always open (100%); software control; keyed access not required
        CONFIG WDTCCS = LFINTOSC        ;WDT reference clock is the 31.0 kHz LFINTOSC
        CONFIG WRT0 = OFF        ;Block 0 (000800-003FFFh) not write-protected
        CONFIG WRT1 = OFF        ;Block 1 (004000-007FFFh) not write-protected
        CONFIG WRT2 = OFF        ;Block 2 (008000-00BFFFh) not write-protected
        CONFIG WRT3 = OFF        ;Block 3 (00C000-00FFFFh) not write-protected
        CONFIG WRT4 = OFF        ;Block 4 (010000-013FFFh) not write-protected
        CONFIG WRT5 = OFF        ;Block 5 (014000-017FFFh) not write-protected
        CONFIG WRT6 = OFF        ;Block 6 (018000-01BFFFh) not write-protected
        CONFIG WRT7 = OFF        ;Block 7 (01C000-01FFFFh) not write-protected
        CONFIG WRTC = OFF        ;Configuration registers (300000-30000Bh) not write-protected
        CONFIG WRTB = OFF        ;Boot Block (000000-0007FFh) not write-protected
        CONFIG WRTD = OFF        ;Data EEPROM not write-protected
        CONFIG SCANE = ON        ;Scanner module is available for use, SCANMD bit can control the module
        CONFIG LVP = OFF        ;HV on MCLR/VPP must be used for programming
        CONFIG CP = OFF            ;UserNVM code protection disabled
        CONFIG CPD = OFF        ;DataNVM code protection disabled
        CONFIG EBTR0 = OFF        ;Block 0 (000800-003FFFh) not protected from table reads executed in other blocks
        CONFIG EBTR1 = OFF        ;Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
        CONFIG EBTR2 = OFF        ;Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
        CONFIG EBTR3 = OFF        ;Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
        CONFIG EBTR4 = OFF        ;Block 4 (010000-013FFFh) not protected from table reads executed in other blocks
        CONFIG EBTR5 = OFF        ;Block 5 (014000-017FFFh) not protected from table reads executed in other blocks
        CONFIG EBTR6 = OFF        ;Block 6 (018000-01BFFFh) not protected from table reads executed in other blocks
        CONFIG EBTR7 = OFF        ;Block 7 (01C000-01FFFFh) not protected from table reads executed in other blocks
        CONFIG EBTRB = OFF        ;Boot Block (000000-0007FFh) not protected from table reads executed in other blocks
    #ENDCONFIG
    
    DEFINE OSC 8
    
    
    PWMVal  var byte
    PWMFreq        con 1000
    W3Val   var byte
    
    TCH con $F8     ' 1mSec
    TCL con $30     '
    
    DEFA    CON $B0
    DIRA    CON $0F
    DEFB    CON $33
    DIRB    CON $23
    DEFC    CON $0
    DIRC    CON $A3
    DEFD    CON $28
    DIRD    CON $27
    DEFE    CON $71
    DIRE    CON $8
    DEFF    CON $FF
    DIRF    CON $DF
    DEFG    CON $10
    DIRG    CON $4
    
    W3      var LATA.6     ' W3
    
    INCLUDE "DT_INTS-18_3_4b.pbp"     ' Base Interrupt System
    INCLUDE "ReEnterPBP-18.pbp"     ' Include if using PBP interrupts
    
    
    ASM
    INT_LIST  macro    ; IntSource,        Label,  Type, ResetFlag?
            INT_Handler   INT0_INT,  _EXTINT,   PBP,  yes
            INT_Handler   TMR0_INT,  _Timer0INT,   PBP,  yes
            INT_Handler   RX1_INT,  _ESPRXin,      PBP,  yes
            INT_Handler   RX2_INT,  _LR3RXin,      PBP,  yes
            INT_Handler   TX1_INT,  _ESPTXOut,     PBP,  yes
            INT_Handler   TX2_INT,  _LR3TXOut,     PBP,  yes
        endm
        INT_CREATE               ; Creates the interrupt processor
    
    ENDASM
    
        goto Start:
    
    EXTINT:
    
    @ INT_RETURN
    
    Timer0INT:
        TMR0H = TCH
        TMR0L = TCL
    
    @ INT_RETURN
    
    ESPRXin:
    
    @ INT_RETURN
    
    ESPTXOut:
    
    @ INT_RETURN
    
    LR3RXin:
    
    @ INT_RETURN
    
    LR3TXOut:
    
    @ INT_RETURN
    
    start:
        Clear
    
        ' PMD Init    
        PMD0 = 0           ' everything ON  for now
        PMD1 = 0           ' everything ON
        PMD2 = 0           ' everything ON
        PMD3 = 0           ' everything ON
        PMD4 = 0           ' everything ON
        PMD5 = 0           ' everything ON
    
        ' ANSEL init
        ANSELD = 0
        ANSELB = 0
        ANSELE = 0
        ANSELG = 0
        ANSELF = 0
        ANSELA = $f     ' Analog on An0 - An3
    
        PORTA = DEFA
        TRISA = DIRA
    
        PORTB = DEFB
        TRISB = DIRB
    
        PORTC = DEFC
        TRISC = DIRC
    
        PORTD = DEFD
        TRISD = DIRD
    
        PORTE = DEFE
        TRISE = DIRE
    
        PORTF = DEFF
        TRISF = DIRF
    
        PORTG = DEFG
        TRISG = DIRG
    
        TRISH = $ff
    
    
        ' WPU init        
        WPUD = 0
        WPUF = 0
        WPUE = 0
        WPUB = 0
        WPUG = 0
        WPUA = 0
        WPUC = 0
        WPUH = 0
    
        ' ODCON init        
        ODCONE = 0
        ODCONF = 0
        ODCONA = 0
        ODCONG = 0
        ODCONB = 0
        ODCONH = 0
        ODCONC = 0
        ODCOND = 0
    
        ' Unlock ?    
        ' PPS Init
        RC6PPS = $0C    ' RC6->EUSART1:TX1    
        RG1PPS = $0E    ' RG1->EUSART2:TX2    
        RX2PPS = $32    ' RG2->EUSART2:RX2    
        RG3PPS = $08    ' RG3->CCP4:CCP4    
        RX1PPS = $17    ' RC7->EUSART1:RX1      
        ' Lock ?
    
        ' Oscillator Init    
        OSCCON1 = $60
    
        OSCCON3 = $00
        OSCEN = 0
        OSCFRQ = 3
    
        ' tmr0 iNIT
        T0CON1 = $40
        TMR0H = TCH
        TMR0L = TCL
        T0CON0 = $90
    
        ' USART 1 Init
        BAUD1CON = $8
        RC1STA = $90
        TX1STA = $24
        SP1BRGL = $67
        SP1BRGH = $0
    
        ' USART 1 Init
        BAUD2CON = $8
        RC2STA = $90
        TX2STA = $24
        SP2BRGL = $67
        SP2BRGH = $00
        W3Val = 0
    
    @ INT_ENABLE  TMR0_INT
    @ INT_ENABLE  RX1_INT
    @ INT_ENABLE  INT0_INT
    @ INT_ENABLE  RX2_INT
    @ INT_ENABLE  TX1_INT
    @ INT_ENABLE  TX2_INT
    
    testser:
        ' hserout2["Test 1 2 3 4",13,10]
        ' hserout["Test 1 2 3 4",13,10]
        pause 1000
        goto Testser
    
        end
    Also I will need the MC bootloader for this project. I also could not download the umc_loader_k40 to try out.

    Thanks for your help.
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