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TMR0 Issue with 18F26K83

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  • Andy Wood
    replied
    Hi Charles,

    The new beta version has fixed the problems I was having with both TMR0 and also the DEC modifier.

    Thanks!

    Andy

    Leave a comment:


  • Charles Leo
    replied
    I've published a beta version for PBP 3.1.2 at http://pbp3.com/downloads/PBP3_312Beta_20190218.exe

    The modified program above worked when I tested it.

    Leave a comment:


  • Charles Leo
    replied
    I'm testing code and I'm not getting the expected results either. Looks like there's a discrepancy between the datasheet and Microchip's header files. I'll post here when I have a fix.

    It's the bit-test IF/THEN that isn't working, though there other problems in the code.

    Code:
    if PIR3.7 = 1 then
    Microchip changed the name of a bit in the STATUS SFR. The datasheet still shows the old name. This will also affect the K42 devices.

    I'll resume in the morning.

    Leave a comment:


  • DavidP
    replied
    Andy, One last thing to try, set bit 7 of OCSEN to a 1 and see if that works.

    Leave a comment:


  • Andy Wood
    replied
    I am still battling with this MCU however I haven't progressed very far.

    During my search for information I came across this post on another forum. Is it possible there are similar issues at play here?

    https://forum.mikroe.com/viewtopic.p...e3410fd8b621f1

    Andy

    Leave a comment:


  • Andy Wood
    replied
    Sorry.. I don't know why it is truncating?

    Please view page 275 of the current data sheet (I can't seem to post the information for whatever reason..)

    The information in the footnote appears to contradict the setting information. Just to be sure, I tried PMD0.7=0 and PMD0.7=1 - there was no difference.

    The clock is a 16MHz crystal and 4xPLL is used to attain 64MHz.The crystal accuracy is required for reliable operation of CAN at 250 kBit/s.

    Andy

    Leave a comment:


  • Andy Wood
    replied
    The board has truncated some of my previous post - so I'll try posting some of the information within code brackets:

    [code]
    SYSCMD: Disable Peripheral System Clock Network bit(1)
    See description in Section 19.4

    Leave a comment:


  • Andy Wood
    replied
    The board has truncated some of my previous post - so I'll try posting some of the information within code brackets:

    [code]
    SYSCMD: Disable Peripheral System Clock Network bit(1)
    See description in Section 19.4

    Leave a comment:


  • Andy Wood
    replied
    Hi David,

    I have tried your suggestion of setting PMD0.7=0 and there is no change. Interestingly, on page 275 of the current datasheet, there is a footnote for SYSCMD:

    SYSCMD: Disable Peripheral System Clock Network bit(1)
    See description in Section 19.4

    Leave a comment:


  • DavidP
    replied
    Also Andy I set these registers after setting the config registers when running 64Mhz.

    CONFIG FEXTOSC = OFF ;HS (crystal oscillator) above 8 MHz; PFM set to high power
    CONFIG RSTOSC = HFINTOSC_64MHZ ;EXTOSC operating per FEXTOSC bits (device manufacturing default)

    OSCCON1 = %00000000 '64 Mhz. INTERNAL Clock
    OSCCON2 = %00000000
    OSCFRQ = %00001000 'SET INTOSC FREQ TO 64 Mhz.
    OSCEN = %01000000 'INTOSC EXPLICIDLY ENABLED

    Leave a comment:


  • DavidP
    replied
    Andy, All looks good but just for grin's also set the SYSCMD bit in PMD0 = 0. This enables the FOSC clock to all peripherals. It should be cleared on reset but?

    Also Andy i notice that you have both OSC circuits enabled:
    CONFIG FEXTOSC = HS ;HS (crystal oscillator) above 8 MHz; PFM set to high power CONFIG RSTOSC = EXTOSC_4PLL ;EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits

    Which one are you intending on using? When I run the intermal 64 Mhz oscillator I set up my config's like this:

    CONFIG FEXTOSC = OFF ;HS (crystal oscillator) above 8 MHz; PFM set to high power
    CONFIG RSTOSC = HFINTOSC_64MHZ ;EXTOSC operating per FEXTOSC bits (device manufacturing default)

    Leave a comment:


  • Andy Wood
    replied
    Hi Dave,

    I really appreciate the input.

    I have tried your suggestions but still no go.

    Modified code is below.





    Code:
      #CONFIG
        CONFIG FEXTOSC = HS        ;HS (crystal oscillator) above 8 MHz; PFM set to high power
        CONFIG RSTOSC = EXTOSC_4PLL        ;EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits
        CONFIG CLKOUTEN = OFF        ;CLKOUT function is disabled
        CONFIG PR1WAY = OFF        ;PRLOCK bit can be set and cleared repeatedly
        CONFIG CSWEN = ON        ;Writing to NOSC and NDIV is allowed
        CONFIG FCMEN = OFF        ;Fail-Safe Clock Monitor disabled
        CONFIG MCLRE = EXTMCLR        ;If LVP = 0, MCLR pin is MCLR; If LVP = 1, RE3 pin function is MCLR
        CONFIG PWRTS = PWRT_64        ;PWRT set at 64ms
        CONFIG MVECEN = OFF        ;Interrupt contoller does not use vector table to prioritze interrupts
        CONFIG IVT1WAY = OFF        ;IVTLOCK bit can be cleared and set repeatedly
        CONFIG LPBOREN = OFF        ;ULPBOR disabled
        CONFIG BOREN = ON        ;Brown-out Reset enabled according to SBOREN
        CONFIG BORV = VBOR_245        ;Brown-out Reset Voltage (VBOR) set to 2.45V
        CONFIG ZCD = OFF        ;ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON
        CONFIG PPS1WAY = OFF        ;PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence)
        CONFIG STVREN = ON        ;Stack full/underflow will cause Reset
        CONFIG DEBUG = OFF        ;Background debugger disabled
        CONFIG XINST = OFF        ;Extended Instruction Set and Indexed Addressing Mode disabled
        CONFIG WDTCPS = WDTCPS_31        ;Divider ratio 1:65536; software control of WDTPS
        CONFIG WDTE = OFF        ;WDT Disabled; SWDTEN is ignored
        CONFIG WDTCWS = WDTCWS_7        ;window always open (100%); software control; keyed access not required
        CONFIG WDTCCS = LFINTOSC        ;WDT reference clock is the 31.0 kHz LFINTOSC
        CONFIG BBSIZE = BBSIZE_512        ;Boot Block size is 512 words
        CONFIG BBEN = OFF        ;Boot block disabled
        CONFIG SAFEN = OFF        ;SAF disabled
        CONFIG WRTAPP = OFF        ;Application Block not write protected
        CONFIG WRTB = OFF        ;Configuration registers (300000-30000Bh) not write-protected
        CONFIG WRTC = OFF        ;Boot Block (000000-0007FFh) not write-protected
        CONFIG WRTD = OFF        ;Data EEPROM not write-protected
        CONFIG WRTSAF = OFF        ;SAF not Write Protected
        CONFIG LVP = OFF        ;HV on MCLR/VPP must be used for programming
        CONFIG CP = OFF        ;PFM and Data EEPROM code protection disabled
      #ENDCONFIG
    
    '-------------------------------------------------------------------------------
    
    DEFINE OSC 64
    
    ' -- Inputs
    
    
    ' -- Outputs
    LedD7       var LATC.1
    LedD5       var LATC.3
    LedD3       var LATC.5
    
    
    
    ' -- Variables
    
    
    
    ' -- Constants
    
    
        clear
    
        ANSELA=0
        ANSELB=0
        ANSELC=0
    
    
        TRISA =  %00000000    '
        TRISB =  %00001000    '
        TRISC =  %10000000  '
    
    
        T0CON0.0 = 0        ' Postscaler = 1:1
        T0CON0.1 = 0
        T0CON0.2 = 0
        T0CON0.3 = 0
    
        T0CON0.4 = 1        ' TMR0 is a 16-bit timer
        T0CON1=%01010101    ' Source=Fosc/4, The input to the TMR0 counter is not synchronized to system clocks, Prescaler=1:32
        PMD1.0 = 0          ' 0 = TMR0 module enabled
        PIR3.7 = 0          ' Clear Timer0 Interrupt flag
        PIE3.7 = 0          ' Enable Timer0 interrupts
    
    
        TMR0H=$3C           '15536 Decimal - Interrupt freq 10Hz with 64MHz clk
        TMR0L=$B0
        T0CON0.7 = 1        ' TMR0 module is enabled and operating
    
    
    
    main:    
        if PIR3.7 = 1 then
            PIR3.7=0        ' Clear TMR0 Interrupt Flag
            T0CON0.7 = 0    ' TMR0 module is is disabled and in the lowest power mode
            TMR0H=$3C       ' Reload Timer
            TMR0L=$B0
            T0CON0.7 = 1    ' TMR0 module is enabled and operating
            toggle ledd5
        endif           
    
        goto main

    Leave a comment:


  • DavidP
    replied
    Well Andy, there is no need for the lines:

    INTCON0.7 = 1 ' Enables all unmasked interrupts
    INTCON0.6 = 1 ' Enables all unmasked low priority interrupts, GIEH also needs to be set for low priority interrupts

    as you have NO interrupt routine written. You are checking the interrupt bit in your loop. It may be vectoring to the interrupt vector and finding nothing there. I would also stop the timer from running before I reloaded the timer registers and then restart the timer.

    Leave a comment:


  • Andy Wood
    replied
    Hi David,

    The Led wont flash. I have checked the hardware is good by writing a simple program to flash the Led. This is the same hardware as my other post about the DEC modifier. The hardware is running the CAN network and associated bits ok so I presume it is good.

    This problem was actually the start of the previous problem as I was wanting to send the current values of TMR0H & TMR0L via the serial port - and then I discovered the DEC modifier didn't work.

    Andy

    Leave a comment:


  • DavidP
    replied
    Well Andy, What isn't it doing before I look at the code?

    Leave a comment:

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