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**FRAN2000** · 07-01-2016, 09:40 AM

As information

As information, the hardware is correct.
I used a 16F876 and boot loader and icd work ok.

Regards
Fran

**richard** · 07-01-2016, 03:18 PM

#CONFIG
CONFIG FOSC = HSHP ; Internal oscillator block
CONFIG PLLCFG = ON ; Oscillator used directly
CONFIG PRICLKEN = ON
CONFIG FCMEN = ON ; Fail-Safe Clock Monitor disabled
CONFIG IESO = OFF ; Oscillator Switchover mode disabled

'DEFINES-----------------------------------------------------------------
DEFINE OSC 20
DEFINE LOADER_USED 1

that's not technically valid , max input to pll is 4 MHz . so with a 4 MHz xtal max osc possible is 16 MHz
if you have a 20 MHz xtal then pll must be off

**Charles Leo** · 07-02-2016, 08:35 AM

I think the first task is to prove that the oscillator is running as expected. White a short "blink" routine using the same configuration, program it directly (no bootloader, no icd), then verify the pause times with an oscilloscope.

I use the following for operation at 64MHz from the internal oscillator:

Code:

' Calibrate PBP to 64MHz clock
DEFINE OSC 64
' Set system clock to 64MHz internal
OSCTUNE.6 = 1
OSCCON = %01110000

  #CONFIG
    CONFIG  FOSC = INTIO67        ; Internal oscillator block
    CONFIG  PLLCFG = ON	    ;Oscillator multiplied by 4
    CONFIG  PRICLKEN = OFF        ; Primary clock can be disabled by software
    CONFIG  FCMEN = OFF           ; Fail-Safe Clock Monitor disabled
    CONFIG  IESO = OFF            ; Oscillator Switchover mode disabled
    CONFIG  PWRTEN = OFF          ; Power up timer disabled
    CONFIG  BOREN = ON	    ;Brown-out Reset enabled and controlled by software (SBOREN is enabled)
    CONFIG  BORV = 285	    ;VBOR set to 2.85 V nominal
    CONFIG  WDTEN = ON            ; WDT is always enabled. SWDTEN bit has no effect
    CONFIG  WDTPS = 32768         ; 1:32768
    CONFIG  CCP2MX = PORTC1       ; CCP2 input/output is multiplexed with RC1
    CONFIG  PBADEN = OFF          ; PORTB<5:0> pins are configured as digital I/O on Reset
    CONFIG  CCP3MX = PORTB5       ; P3A/CCP3 input/output is multiplexed with RB5
    CONFIG  HFOFST = ON           ; HFINTOSC output and ready status are not delayed by the oscillator stable status
    CONFIG  T3CMX = PORTC0        ; T3CKI is on RC0
    CONFIG  P2BMX = PORTB5        ; P2B is on RB5
    CONFIG  MCLRE = EXTMCLR       ; MCLR pin enabled, RE3 input pin disabled
    CONFIG  STVREN = ON           ; Stack full/underflow will cause Reset
    CONFIG  LVP = OFF             ; Single-Supply ICSP disabled
    CONFIG  XINST = OFF           ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
    CONFIG  DEBUG = OFF           ; Disabled
  #ENDCONFIG

**FRAN2000** · 07-02-2016, 09:28 AM

Hi, thanks for your reply.

Hi, thanks for your reply.

If I transfer the program to the boot loader without icd the program and the microprocessor works ok. for example lighting a led.

Probare suggesting this and tell me the result.

Thank you very much.

**richard** · 07-02-2016, 07:41 PM

Charles
I was trying to work through this problem with fran2000's icd but have just discovered that since my laptop ugraded itself to win10 that mscpx will no longer allow icd compiles for anything but the basic mscx pic chips . have reinstalled it twice with no improvement .

Order#: 37376

make that 3 times now , tried an uninstall ... still no go

**Henrik Olsson** · 07-02-2016, 11:28 PM

Hi,
Juming in late here and may be stating the obvious but, generally, when a bootloader is used IT is what's setting the oscillator option (such as oscillator type (INT, HS etc) PLL on/off etc) and the other CONFIG bits so including a CONFIG block in the code which is to be downloaded via a bootloader doesn't make sense to me. It might depend on the bootloader, I don't know but the OP doesn't state which one is being used. Then again, if the CONFIG block in the code is the same as that of the bootloader then the above is not part of the problem.

/Henrik.

**FRAN2000** · 07-03-2016, 01:13 AM

Hello

Hello, thank you all for the help.

I have to check what richard suggests to me, but is very rare.

I have long been using the boot loader and the icd with 16F876 and if the boot loader works once compiled icd icd works well.

in this case I had never happened that the boot loader work and icd no.

unless that icd models generator malfunction. 18F .. not in the default list of devices and built it with icd mcsx generator models. keep trying.

Another thing, for example, once compiled with icd for the 16F876 when you hit the button to run the icd, a message appears to restart the microprocessor.

When you compile with the icd for the model 18 .. and you press the button to run the icd, this message does not appear. Only it appears out of time.

Someone used this micro with ICD?

Fran

**richard** · 07-03-2016, 02:33 AM

did you watch dt's video on icd model generation ?

http://support.melabs.com/DT/INTOSC_ICD/INTOSC_ICD.html

pay particular attention to disabling analog attributes for tx/rx eusart pins in the model file
that what I was going to look at before my mcspx started to play up

**FRAN2000** · 07-03-2016, 03:10 AM

hello

Hello, in principle are disabled here:

ADCON0.0 = 0 'Disable ADC
ANSELA = 0
ANSELB = 0
ANSELC = 0
CM1CON0.7 = 0 'Disable comparator1
CM2CON0.7 = 0 'Disable comparator2

I think this ok.

The pic I use is the 28 pin. using the port c6, c7

If someone thinks that something is missing to disable, but I do not see it.

Fran

**richard** · 07-03-2016, 03:54 AM

ok I got mcspx to work again , it was a id10t error I placed the created icd model in the wrong folder

tried this model file but now get "different address ....... " error using int osc @64mhz

at least its no the timeout error

Code:

 example custom  baudrate => OSC = 64
#ifdef _OSC_64
OSCCON=$70
OSCTUNE.6=1
BAUDCON.3 = 1 
RCSTA1 = $90   ' Enable serial port & continuous receive       
TXSTA1 = $24   ' Enable transmit, BRGH = 1
SPBRG1 = 130   ' 9600 Baud @ 64MHz, -0.02%
SPBRGH1 = 6
define HSER_BAUD  9600
#define ICD_BAUDRATE_SET
#endif

tried all sorts of baud rates

still trying

Attached Files

18f26k22_ICD_PBPX .txt (7.6 KB, 204 views)

**FRAN2000** · 07-03-2016, 02:08 PM

Hello

Interestingly, we also think it can be problem of the configuration file builder icd models.

Something is not right. possibly.

What would be very useful to know if someone operated this 18f .. with the icd.

**richard** · 07-03-2016, 05:11 PM

solved yeh !

seems you need to make sure the osc is stable and pll is ready before icd code starts up

Code:

 ******************* USER INITIALISATION CODE *******************
' some devices have specific requirements - for example, making 
' the USART pins digital - use this section to add your custom 
' code...
' <== ADD CODE HERE
ANSELC=0
while ! osccon2.7 ; wait for pll ready
 wend

osc block

Code:

#ifdef _OSC_64
OSCCON=$70
OSCTUNE.6=1
define HSER_BAUD  115200 
define MULT       16 
define HSER_SPBRG ((OSC * 1000000 / HSER_BAUD + (MULT / 2)) / MULT - 1)
#define ICD_BAUDRATE_SET
#endif

**FRAN2000** · 07-04-2016, 12:43 AM

Hello

Hi, I modified my file and it does not work.

This is the program, and the modified file is attached

#CONFIG
CONFIG FOSC = INTIO67 ; Internal oscillator block
CONFIG PLLCFG = ON ;Oscillator multiplied by 4
CONFIG PRICLKEN = OFF ; Primary clock can be disabled by software
CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor disabled
CONFIG IESO = OFF ; Oscillator Switchover mode disabled
CONFIG PWRTEN = OFF ; Power up timer disabled
CONFIG BOREN = ON ;Brown-out Reset enabled and controlled by software (SBOREN is enabled)
CONFIG BORV = 285 ;VBOR set to 2.85 V nominal
CONFIG WDTEN = ON ; WDT is always enabled. SWDTEN bit has no effect
CONFIG WDTPS = 32768 ; 1:32768
CONFIG CCP2MX = PORTC1 ; CCP2 input/output is multiplexed with RC1
CONFIG PBADEN = OFF ; PORTB<5:0> pins are configured as digital I/O on Reset
CONFIG CCP3MX = PORTB5 ; P3A/CCP3 input/output is multiplexed with RB5
CONFIG HFOFST = ON ; HFINTOSC output and ready status are not delayed by the oscillator stable status
CONFIG T3CMX = PORTC0 ; T3CKI is on RC0
CONFIG P2BMX = PORTB5 ; P2B is on RB5
CONFIG MCLRE = EXTMCLR ; MCLR pin enabled, RE3 input pin disabled
CONFIG STVREN = ON ; Stack full/underflow will cause Reset
CONFIG LVP = OFF ; Single-Supply ICSP disabled
CONFIG XINST = OFF ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
CONFIG DEBUG = OFF ; Disabled
#ENDCONFIG

'DEFINES-----------------------------------------------------------------
DEFINE OSC 64
DEFINE LOADER_USED 1

ADCON0.0 = 0 'Disable ADC
ANSELA = 0
ANSELB = 0
ANSELC = 0
CM1CON0.7 = 0 'Disable comparator1
CM2CON0.7 = 0 'Disable comparator2

' Set system clock to 64MHz internal
OSCTUNE.6 = 1
OSCCON = %01110000

'------------------------------------------------------------------------------
'PROCESO PRINCIPAL-------------------------------------------------------------
PROCESOPRINCIPAL:

GOTO PROCESOPRINCIPAL
END
'-------------------------------------------------------------
'------------------------------------------------------------------------------

I think I've put everything right.
Regards

Fran

Attached Files

18_ICD_PBPX.bas.txt (7.6 KB, 238 views)

**FRAN2000** · 07-04-2016, 12:53 AM

hello

Wait, I'm sorry I have not not create the model again.

Upss..

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Help 18f26k22 and icd no work

Help 18f26k22 and icd no work

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